The increased integration of multiple-cores and large shared caches in microprocessors may require improved energy-efficiency for core-to-core, core-to-cache and intra-core communication to sustain desired performance benefits within shrinking power envelopes.
The cycle time for a communication bus may be based on wire pitch, repeater sizes and worst-case switching activity. Worst-case switching activity for a communication path such as, by way of example and not by way of limitation, on an unshielded static bus, may involve neighboring wires switching simultaneously in opposite direction which may result in maximizing the Miller Coupling Factor for inter-wire coupling capacitance.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding or analogous elements.